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Addrecat.adoecat.sub1.adoecat.sub2.adoecat.sub3.adoecat.sub4.adoecat.sub5.adoecat.sub6.adoecat.sub7.adoecat.sub8.adoecat.sub9.adoecat.sub10.adoLog Addrecat.ladecat.sub1.ladecat.sub2.ladecat.sub3.ladecat.sub4.ladecat.sub5.ladecat.sub6.ladecat.sub7.ladecat.sub8.ladecat.sub9.ladecat.sub10.ladInterruptecat.intDC D-Aecat.dc.dif.daDC B-Decat.dc.dif.bdDC C-Becat.dc.dif.cbDC C-Decat.dc.dif.cdDC B-Aecat.dc.dif.baDC C-Aecat.dc.dif.caecat.sub1.dc.dif.daecat.sub2.dc.dif.daecat.sub3.dc.dif.daecat.sub4.dc.dif.daecat.sub5.dc.dif.daecat.sub6.dc.dif.daecat.sub7.dc.dif.daecat.sub8.dc.dif.daecat.sub9.dc.dif.daecat.sub10.dc.dif.daDC B-Cecat.sub1.dc.dif.bdecat.sub2.dc.dif.bdecat.sub3.dc.dif.bdecat.sub4.dc.dif.bdecat.sub5.dc.dif.bdecat.sub6.dc.dif.bdecat.sub7.dc.dif.bdecat.sub8.dc.dif.bdecat.sub9.dc.dif.bdecat.sub10.dc.dif.bdecat.sub1.dc.dif.cbecat.sub2.dc.dif.cbecat.sub3.dc.dif.cbecat.sub4.dc.dif.cbecat.sub5.dc.dif.cbecat.sub6.dc.dif.cbecat.sub7.dc.dif.cbecat.sub8.dc.dif.cbecat.sub9.dc.dif.cbecat.sub10.dc.dif.cbecat.sub1.dc.dif.cdecat.sub2.dc.dif.cdecat.sub3.dc.dif.cdecat.sub4.dc.dif.cdecat.sub5.dc.dif.cdecat.sub6.dc.dif.cdecat.sub7.dc.dif.cdecat.sub8.dc.dif.cdecat.sub9.dc.dif.cdecat.sub10.dc.dif.cdecat.sub1.dc.dif.baecat.sub2.dc.dif.baecat.sub3.dc.dif.baecat.sub4.dc.dif.baecat.sub5.dc.dif.baecat.sub6.dc.dif.baecat.sub7.dc.dif.baecat.sub8.dc.dif.baecat.sub9.dc.dif.baecat.sub10.dc.dif.baecat.sub1.dc.dif.caecat.sub2.dc.dif.caecat.sub3.dc.dif.caecat.sub4.dc.dif.caecat.sub5.dc.dif.caecat.sub6.dc.dif.caecat.sub7.dc.dif.caecat.sub8.dc.dif.caecat.sub9.dc.dif.caecat.sub10.dc.dif.caecat.subframe.lengthecat.subframe.reservedRound tripecat.subframe.circulatingLast indicatorecat.subframe.morePad bytesecat.subframe.pad_bytesESC Revision (0x0)ecat.reg.revisionESC Type (0x1)ecat.reg.typeESC Build (0x2)ecat.reg.buildESC FMMU Cnt (0x4)ecat.reg.fmmucntESC SM Cnt (0x5)ecat.reg.smcntESC Ports (0x6)ecat.reg.portsESC DPRAM (0x7)ecat.reg.dpramESC Features (0x8)ecat.reg.featuresFMMU bytewise restrictionSM addressing restrictionDC supportecat.reg.features.dcsupportDC 64 bit supportecat.reg.features.dc64supportE-Bus low jitterE-Bus ext. link detectionMII ext. link detectionCRC ext. detectionecat.reg.features.crcextPhys Addr (0x10)ecat.reg.physaddrPhys Addr 2nd (0x12)ecat.reg.physaddr2ESC Ctrl (0x100)ecat.reg.dlctrl1Kill non EtherCAT framesecat.reg.dlctrl1.killnonecatPort 0 ext. link detectionPort 1 ext. link detectionPort 2 ext. link detectionPort 3 ext. link detectionESC Ctrl (0x101)ecat.reg.dlcrtl2ecat.reg.dlcrtl2.port0ecat.reg.dlcrtl2.port1ecat.reg.dlcrtl2.port2ecat.reg.dlcrtl2.port3ESC Ctrl (0x102)ecat.reg.dlctrl3Fifo sizeecat.reg.dlctrl3.fifosizeLow E-Bus jitterecat.reg.dlctrl3.lowebusjitESC Ctrl (0x103)ecat.reg.dlctrl4Second addressecat.reg.dlctrl4.2ndaddressESC Status (0x110)ecat.reg.dlstatus1Operationecat.reg.dlstatus1.operationPDI watchdogEnh. Link DetectionPhysical link Port 0Physical link Port 1Physical link Port 2Physical link Port 3ESC Status (0x111)ecat.reg.dlstatus2ecat.reg.dlstatus2.port0ecat.reg.dlstatus2.port1ecat.reg.dlstatus2.port2ecat.reg.dlstatus2.port3Write Register Protect (0x20)ecat.reg.regprotectAccess Protect (0x30)ecat.reg.accessprotectESC reset Ecat (0x40)ecat.reg.resetecatESC reset Pdi (0x41)ecat.reg.resetpdiPhys. RW Offset (0x108)ecat.regphysrwoffsAL Ctrl (0x120)ecat.reg.alctrlAl Ctrlecat.reg.alctrl.ctrlError Ackecat.reg.alctrl.errackecat.reg.alctrl.idAL Status (0x130)ecat.reg.alstatusAl Statusecat.reg.alstatus.statusecat.reg.alstatus.errecat.reg.alstatus.idAL Status Code (0x134)ecat.reg.alstatuscodePDI Ctrl (0x140)ecat.reg.pdictrl1ecat.reg.pdictrl1.pdiPDI Ctrl (0x141)ecat.reg.pdictrl2Device emulationecat.reg.pdictrl2.devemulEnhanced link detectionEnable DC sync outecat.reg.pdictrl2.dcsyncoutEnable DC latch inecat.reg.pdictrl2.dcsyncinECAT IRQ Mask (0x200)ecat.reg.irqmask.ecat_maskLatch eventESC Status eventAL Status eventSM 0 IRQSM 1 IRQSM 2 IRQSM 3 IRQSM 4 IRQSM 5 IRQSM 6 IRQSM 7 IRQPDI IRQ Mask L (0x204)ecat.reg.irqmask.pdiLAL Ctrlecat.reg.irqmask.pdiL.alctrlLatch inputecat.reg.irqmask.pdiL.latchinecat.reg.irqmask.pdiL.sync0ecat.reg.irqmask.pdiL.sync1SM changedecat.reg.irqmask.pdiL.smchgEEPROM command pendingSM 0ecat.reg.irqmask.pdiL.sm0SM 1ecat.reg.irqmask.pdiL.sm1SM 2ecat.reg.irqmask.pdiL.sm2SM 3ecat.reg.irqmask.pdiL.sm3SM 4ecat.reg.irqmask.pdiL.sm4SM 5ecat.reg.irqmask.pdiL.sm5SM 6ecat.reg.irqmask.pdiL.sm6SM 7ecat.reg.irqmask.pdiL.sm7PDI IRQ Mask H (0x206)ecat.reg.irqmask.pdiHECAT IRQ (0x210)ecat.reg.irq.ecatecat.reg.irq.ecat.latchevtecat.reg.irq.ecat.escstatevtecat.reg.irq.ecat.alstatevtecat.reg.irq.ecat.sm0irqecat.reg.irq.ecat.sm1irqecat.reg.irq.ecat.sm2irqecat.reg.irq.ecat.sm3irqecat.reg.irq.ecat.sm4irqecat.reg.irq.ecat.sm5irqecat.reg.irq.ecat.sm6irqecat.reg.irq.ecat.sm7irqPDI IRQ 1 (0x220)ecat.reg.irq.pdi1ecat.reg.irq.pdi1.alctrlecat.reg.irq.pdi1.latchinecat.reg.irq.pdi1.sync0ecat.reg.irq.pdi1.sync1ecat.reg.irq.pdi1.smchgecat.reg.irq.pdi1.sm0ecat.reg.irq.pdi1.sm1ecat.reg.irq.pdi1.sm2ecat.reg.irq.pdi1.sm3ecat.reg.irq.pdi1.sm4ecat.reg.irq.pdi1.sm5ecat.reg.irq.pdi1.sm6ecat.reg.irq.pdi1.sm7PDI IRQ 2 (0x222)ecat.reg.irq.pdi2CRC 0 (0x300)ecat.reg.crc0CRC 1 (0x302)ecat.reg.crc1CRC 2 (0x304)ecat.reg.crc2CRC 3 (0x306)ecat.reg.crc3Invalid frameecat.reg.crc0.frameRX errorecat.reg.crc0.rxecat.reg.crc1.frameecat.reg.crc1.rxecat.reg.crc2.frameecat.reg.crc2.rxecat.reg.crc3.frameecat.reg.crc3.rxForw. CRC 0 (0x308)ecat.reg.crc.fwd0Forw. CRC 1 (0x309)ecat.reg.crc.fwd1Forw. CRC 2 (0x30A)ecat.reg.crc.fwd2Forw. CRC 3 (0x30B)ecat.reg.crc.fwd3Process unit error (0x30C)ecat.reg.processuniterrPDI error (0x30D)ecat.reg.pdierrLink Lost 0 (0x310)ecat.reg.linklost0Link Lost 1 (0x311)ecat.reg.linklost1Link Lost 2 (0x312)ecat.reg.linklost2Link Lost 3 (0x313)ecat.reg.linklost3WD Divisor (0x400)ecat.reg.wd.divisorWD Time PDI (0x410)ecat.reg.wd.timepdiWD Time SM (0x420)ecat.reg.wd.timesmWD Status (0x440)ecat.reg.wd.statusPD watchdogecat.reg.wd.status.pdwatchdogWD SM Counter (0x442)ecat.reg.wd.cntsmWD PDI Counter (0x443)ecat.reg.wd.cntpdiEEPROM Assign (0x500)ecat.reg.eeprom.assignEEPROM access ctrlecat.reg.eeprom.assign.ctrlReset PDI accessEEPROM access statusecat.reg.eeprom.assign.statusEEPROM Ctrl/Status (0x502)ecat.reg.ctrlstatWrite accessecat.reg.ctrlstat.wraccessEEPROM emulationecat.reg.ctrlstat.eepromemul8 byte accessecat.reg.ctrlstat.8bacc2 byte addressecat.reg.ctrlstat.2baccRead accessecat.reg.ctrlstat.rdaccecat.reg.ctrlstat.wraccReload accessecat.reg.ctrlstat.reloadaccCRC errorecat.reg.ctrlstat.crcerrLoad errorecat.reg.ctrlstat.lderrCmd errorecat.reg.ctrlstat.cmderrWrite errorecat.reg.ctrlstat.wrerrBusyecat.reg.ctrlstat.busyEEPROM Address Lo (0x504)ecat.reg.addrlEEPROM Address Hi (0x506)ecat.reg.addrhEEPROM Data 0 (0x508)ecat.reg.data0EEPROM Data 1 (0x50A)ecat.reg.data1EEPROM Data 2 (0x50c)ecat.reg.data2EEPROM Data 3 (0x50e)ecat.reg.data3Phy MIO Ctrl/Status (0x510)ecat.reg.mio.ctrlstatecat.reg.mio.ctrlstat.wracc1Offset Phy offsetecat.reg.mio.ctrlstat.offsphyecat.reg.mio.ctrlstat.rdaccecat.reg.mio.ctrlstat.wracc2ecat.reg.mio.ctrlstat.wrerrecat.reg.mio.ctrlstat.busyPhy MIO Address (0x512)ecat.reg.mio.addrPhy addressecat.reg.mio.addr.phyaddrMIO addressecat.reg.mio.addr.mioaddrPhy MIO Data (0x514)ecat.reg.mio.dataMIO access (0x516)ecat.reg.mio.accessECAT claims exclusive accessecat.reg.mio.access.ecataccecat.reg.mio.access.pdiaccForce PDI to reset 0517.0MIO port status 0 (0x518)ecat.reg.mio.status0Physical link detectedecat.reg.mio.status0.physlinkLink detectedecat.reg.mio.status0.linkLink status errorRead errorecat.reg.mio.status0.readerrLink partner errorPhy config updatedMIO port status 1 (0x519)ecat.reg.mio.status1ecat.reg.mio.status1.physlinkecat.reg.mio.status1.linkecat.reg.mio.status1.readerrMIO port status 2 (0x51A)ecat.reg.mio.status2ecat.reg.mio.status2.physlinkecat.reg.mio.status2.linkecat.reg.mio.status2.readerrMIO port status 3 (0x51B)ecat.reg.mio.status3ecat.reg.mio.status3.physlinkecat.reg.mio.status3.linkecat.reg.mio.status3.readerrFMMUecat.fmmuLog Startecat.fmmu.lstartLog Lengthecat.fmmu.llenLog StartBitecat.fmmu.lstartbitLog EndBitecat.fmmu.lendbitPhys Startecat.fmmu.pstartPhys StartBitecat.fmmu.pstartbitecat.fmmu.typeecat.fmmu.typereadecat.fmmu.typewriteActivateecat.fmmu.activateecat.fmmu.activate0SyncManagerecat.syncmanSM Startecat.syncman.startSM Lengthecat.syncman.lenSM Ctrl/Statusecat.syncman.ctrlstatusecat.syncman.opmodeecat.syncman.accessECAT IRQecat.syncman.irq.ecatPDI IRQecat.syncman.irq.pdiWatchdog triggerecat.syncman.wdtIRQ writeecat.syncman.irq.writeIRQ readecat.syncman.irq.read1 buffer stateecat.syncman.1bufstate3 buffer stateecat.syncman.3bufstateSM Enableecat.syncman.smenableecat.syncman.enableRepeat requestecat.syncman.repeatreqLatch SyncMan Change ECATecat.syncman.latchsmchg.ecatLatch SyncMan Change PDIecat.syncman.latchsmchg.pdiDeactivateecat.syncman.deactivateRepeat acknowledgeecat.syncman.repeatackDC RecvTime_0 (0x900)ecat.reg.dc.recv0DC RecvTime_1 (0x904)ecat.reg.dc.recv1DC RecvTime_2 (0x908)ecat.reg.dc.recv2DC RecvTime_3 (0x90c)ecat.reg.dc.recv3DC SysTime (0x910)ecat.reg.dc.systimeDC SysTime L (0x910)ecat.reg.dc.systimeLDC SysTime H (0x914)ecat.reg.dc.systimeHDC RecvTime (0x918)ecat.reg.dc.recvtime64DC SysTimeOffs (0x920)ecat.reg.dc.systimeoffsDC SysTimeOffs L (0x920)ecat.reg.dc.systimeoffslDC SysTimeOffs H (0x924)ecat.reg.dc.systimeoffshDC SysTimeDelay (0x928)ecat.reg.dc.systimedelayDC CtrlError (0x92c)ecat.reg.dc.ctrlerrDC SpeedStart (0x930)ecat.reg.dc.speedstartDC SpeedDiff (0x932)ecat.reg.dc.speeddiffecat.reg.dc.fltdepth.speedcntecat.reg.dc.cycunitctrlWrite access cyclicWrite access latch 0Write access latch 1DC Activation (0x981)ecat.reg.dc.activationEnable cyclicGenerate SYNC 0Generate SYNC 1Auto activationStart time extension 32->64Start time chheckHalf rangeDebug pulseDC CycImpulse (0x982)ecat.reg.dc.cycimpulsDC Activation status (0x984)ecat.reg.dc.activationstatSYNC 0 pendingSYNC 1 pendingStart time out of rangeDC Sync0 Status (0x98e)ecat.reg.dc.sync0.statustriggeredDC Sync0 Status1 (0x98f)ecat.reg.dc.sync1.statusDC StartTime0 (0x990)ecat.reg.dc.starttime0DC StartTime1 (0x998)ecat.reg.dc.starttime1DC CycTime0 (0x9a0)ecat.reg.dc.cyctime0DC CycTime1 (0x9a4)ecat.reg.dc.cyctime1DC Latch0 Ctrl (0x9a8)ecat.reg.dc.latch0.ctrlecat.reg.dc.latch0.ctrl.posecat.reg.dc.latch0.ctrl.negDC Latch1 Ctrl (0x9a9)ecat.reg.dc.latch1.ctrlecat.reg.dc.latch1.ctrl.posecat.reg.dc.latch1.ctrl.negDC Latch0 Status (0x9ae)ecat.reg.dc.latch0.statusEvent posEvent negpin stateDC Latch1 Status (0x9af)ecat.reg.dc.latch1.statusDC Latch0 Pos (0x9b0)ecat.reg.dc.latch0.posDC Latch0 Neg (0x9b8)ecat.reg.dc.latch0.negDC Latch1 Pos (0x9c0)ecat.reg.dc.latch1.posDC Latch1 Neg (0x9c8)ecat.reg.dc.latch1.negDC RecvSyncManChange (0x9f0)ecat.reg.dc.rcvsyncmanchgDC PdiSyncManStart (0x9f8)ecat.reg.dc.pdismstartDC PdiSyncManChange (0x9fc)ecat.reg.dc.pdismchgSingle eventContinuous1. buffer2. buffer3. bufferblocked (start)Written3 buffer1 buffer1 buffer directdeactivatedPDI emulates EEPROMNormal operationReset Bit 501.0 to 0Do not change Bit 501.0Local uCNone4 bit dig. input4 bit dig. outputSPI slaveEtherCAT bridge16 bit uC (async)8 bit uC (async)16 bit uC (sync)8 bit uC (sync)32/0 bit dig. in/output24/8 bit dig. in/output16/16 bit dig. in/output8/24 bit dig. in/output0/32 bit dig. in/outputOn chip busPREOPBOOTSTRAPSAFEOPLoop open, no linkLoop closed, no linkLoop open, with linkLoop closed, with linkAuto loopAuto close onlyLoop openLoop closedOkayRun outDisableEnabledDisabledTrueFalseWrite in useWrite ignoreRead in useRead ignoreLast EtherCAT datagramFrame has circulated onceFrame is not circulatingValidNo operationAuto Increment Physical ReadAuto Increment Physical WriteBroadcast ReadBroadcast WriteBroadcast ReadWriteLogical ReadLogical WriteLogical ReadWriteAPRDAPWRAPRWFPRDFPWRFPRWBRDBWRBRWLRDLWRLRWARMWFRMW'%s': Len: %d, Adp 0x%x, Ado 0x%x, Wc %d %d Cmds, '%s': len %d, '%s': len %d %d Cmds, '%s': len %d, '%s': len %d, '%s': len %d%d Cmds, '%s': len %d, '%s': len %d, '%s': len %d, '%s': len %dEtherCAT datagram: Cmd: '%s' (%d), Len: %d, Adp 0x%x, Ado 0x%x, Cnt %dEtherCAT datagram: Cmd: '%s' (%d), Len: %d, Addr 0x%x, Cnt %dEtherCAT datagram: Cmd: 'EXT' (%d), Len: %dEtherCAT datagram: Cmd: 'Unknown' (%d), Len: %dCmd : %d (Unknown command)Length : %d (0x%x) - %s - %sThe working counter is increased once for each addressed device if at least one byte/bit of the data was successfully read and/or written by that device, it is increased once for every operation made by that device - read/write/read and writeecat.reg.features.fmmurestrictecat.reg.features.smaddrrestrictecat.reg.features.ebuslowjitterecat.reg.features.ebusextlinkdetectecat.reg.features.miiextlinkdetectecat.reg.dlctrl1.port0extlinkdetectecat.reg.dlctrl1.port1extlinkdetectecat.reg.dlctrl1.port2extlinkdetectecat.reg.dlctrl1.port3extlinkdetectecat.reg.dlstatus1.pdiwatchdogecat.reg.dlstatus1.enhlinkdetectecat.reg.dlstatus1.physlink.port0ecat.reg.dlstatus1.physlink.port1ecat.reg.dlstatus1.physlink.port2ecat.reg.dlstatus1.physlink.port3ecat.reg.pdictrl2.enhlnkdetectEnhanced link detection port 0ecat.reg.pdictrl2.enhlnkdetect0Enhanced link detection port 1ecat.reg.pdictrl2.enhlnkdetect1Enhanced link detection port 2ecat.reg.pdictrl2.enhlnkdetect2Enhanced link detection port 3ecat.reg.pdictrl2.enhlnkdetect3ecat.reg.irqmask.ecat_mask.latchevtecat.reg.irqmask.ecat_mask.escstatevtecat.reg.irqmask.ecat_mask.alstatevtecat.reg.irqmask.ecat_mask.sm0irqecat.reg.irqmask.ecat_mask.sm1irqecat.reg.irqmask.ecat_mask.sm2irqecat.reg.irqmask.ecat_mask.sm3irqecat.reg.irqmask.ecat_mask.sm4irqecat.reg.irqmask.ecat_mask.sm5irqecat.reg.irqmask.ecat_mask.sm6irqecat.reg.irqmask.ecat_mask.sm7irqecat.reg.irqmask.pdiL.eepromcmdpenecat.reg.irq.pdi1.eepromcmdpenecat.reg.eeprom.assign.pdiaccessPDI has access to MII managementecat.reg.mio.access.forceresetecat.reg.mio.status0.linkstatuserrecat.reg.mio.status0.linkpartnererrecat.reg.mio.status0.phycfgupdatedecat.reg.mio.status1.linkstatuserrecat.reg.mio.status1.linkpartnererrecat.reg.mio.status1.phycfgupdatedecat.reg.mio.status2.linkstatuserrecat.reg.mio.status2.linkpartnererrecat.reg.mio.status2.phycfgupdatedecat.reg.mio.status3.linkstatuserrecat.reg.mio.status3.linkpartnererrecat.reg.mio.status3.phycfgupdatedDC Filter Depth System Time difference (0x934)ecat.reg.dc.fltdepth.systimediffDC Filter Depth Speed counter (0x935)DC Cyclic Unit Control (0x980)ecat.reg.dc.cycunitctrl.access_cyclicecat.reg.dc.cycunitctrl.access_latch0ecat.reg.dc.cycunitctrl.access_latch1ecat.reg.dc.activation.enablecyclicecat.reg.dc.activation.gen_sync0ecat.reg.dc.activation.gen_sync1ecat.reg.dc.activation.autoactivationecat.reg.dc.activation.stimeextecat.reg.dc.activation.stimecheckecat.reg.dc.activation.hlfrangeecat.reg.dc.activation.dblrangeecat.reg.dc.activationstat.sync0pendecat.reg.dc.activationstat.sync1pendecat.reg.dc.activationstat.stimeoutofrangeecat.reg.dc.sync0.status.triggeredecat.reg.dc.sync1.status.triggeredecat.reg.dc.latch0.status.eventposecat.reg.dc.latch0.status.eventnegecat.reg.dc.latch0.status.pinstateecat.reg.dc.latch1.status.eventposecat.reg.dc.latch1.status.eventnegecat.reg.dc.latch1.status.pinstateMore EtherCAT datagrams will followAuto Increment Physical ReadWriteConfigured address Physical ReadConfigured address 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GA*FORTIFYGA+GLIBCXX_ASSERTIONS GA*GOW*GA*cf_protectionGA+omit_frame_pointerGA+stack_clashGA!stack_realign GA*FORTIFYMGA+GLIBCXX_ASSERTIONS GA*FORTIFY@GA+GLIBCXX_ASSERTIONSethercat.so-2.6.2-17.el8.x86_64.debug@v7zXZִF!t/]?Eh=ڊ2N څݞ9"goM㳮ݩ>ظ(کw6·dS,5LOZfnj:˭.%8Ap5hPM,āR7 hZJYYډPw,jRhL~[sWQCh1? 2Xe qIz O ds"L`0q@,+WduhK q2J1%w[ՋB8ܧ(+g'7Td:k|caL6_WxT1-JF4Xf*ֱ xBM|ȅQX7eQxdIR8^ڥfZJv'rVېn[ӆ}G7 Xx(:0֠F@-s7k6%ueFfxo'(Qهڅ5tx8D%¨M%`mIϰҼ06W_:5ij*PdW3\ %=pWLŢYmhI0kv \0zc,Um.FGܶB?tNug 瀓CF\J9mkZΜrcNw`zfx4\CghT;e1@luf Fxw eD6 a1ڲsv}/=xF6ZtwQ͓rl,m [/q0!Ⱥd9?gY㉾x9zAs+n P]>(A ǩ 7P-NۍC@7Ws(H^(6"KPA26ϧ/sJ$ɏ1[.Lx1 E"AZH<}אItݘfhG$rVxUE*~=2Y0CޏEM]r+i4 8y-ϛTC\Q(R9r}7s`P2+I *H,^n2') 5qou.y;] ^Sp]nw{6 (Tm+wPn8a!쨡5N7 2I=)ffK|[w#uAmp3(%ߓ` cr')b6~&4n]Iŀšú lK=LnJ|G,W ^@]Bj/zuhM' )ZT_gYZ.shstrtab.note.gnu.build-id.gnu.hash.dynsym.dynstr.gnu.version.gnu.version_r.rela.dyn.rela.plt.init.plt.sec.text.fini.rodata.eh_frame_hdr.eh_frame.note.gnu.property.init_array.fini_array.data.rel.ro.dynamic.got.data.bss.gnu.build.attributes.gnu_debuglink.gnu_debugdata 88$o``<( 0H H 8o::Eo0Tp.^Bh>h>h D Dc@D@Dn H HwKKe} 22L44<< @"@@"@@"@+ k"k m"m p"p  d#d8 Xecdd th,h0m(